1. Field
Embodiments described herein generally relate to methods of forming a gate in a semiconductor device. More specifically, embodiments described herein relate to methods for reducing the K value of a dielectric layer useful in advanced FinFET formation.
2. Description of the Related Art
In response to an increased need for smaller electronic devices with denser circuits, devices with three dimensional (3D) structures have been developed. An example of such devices may include FinFETs having conductive fin-like structures that are raised vertically above a horizontally extending substrate. Conventional FinFETs may be formed on a substrate, such as a semiconducting substrate or silicon-on-insulator. The substrate may comprise a semiconducting substrate and an oxide layer disposed on the semiconducting substrate.
In light of the continued demand for continually smaller devices, a decreased gate pitch increases the parasitic capacitance for both contact-to-gate and epi-to-gate, thus, increasing the overall gate capacitance. Minimizing the traditional capacitance elements, such as under-lap capacitance, channel capacitance, junction capacitance and inner and outer fringe capacitance is becoming more challenging. Further, gate and contact critical dimensions have been scaling at a slower rate than gate pitch. As a result, parasitic fringe capacitance (contact-to-gate capacitance and epi-to-gate capacitance) is becoming an increasingly significant issue.
Therefore, there is a need in the art for methods for reducing parasitic capacitance in FinFET structures.